1. Field of the Invention
This invention relates to a sense circuit for determining the data state of a memory cell in a multilevel storage system, thereby providing binary output signals.
2. Description of the Related Art
Conventional memory cells store one bit of data, 0 or 1, in the form of one of two possible charge levels. For example, a high charge level may represent the data bit 1, whereas a low charge level may represent the data bit 0. In order to read the stored data, a data input signal is compared to a reference voltage level. The data input signal is at one of two voltage levels determined by which of the two possible charge levels is present in the memory cell. The reference voltage level is set between the two possible voltage levels corresponding to the two possible charge levels of the memory cell. By determining whether the voltage level of the data input signal is higher or lower than the reference voltage level, the data state of the memory cell may be read.
Multilevel storage systems for storing data in the form of more than two possible charge levels have recently become of interest. Such systems increase the amount of data stored per cell, thus potentially increasing the overall storage density of memory systems. A sample multilevel storage system stores several bits of data per memory cell. For example, the four unique states capable of being represented by two data bits (00), (01), (10), and (11) can correspond to the charge levels 0, 2, 4, and 6 charge units respectively. Unfortunately, the sense scheme necessary to read the data stored in a memory cell becomes more complex as more data is stored in the cell. A single reference voltage level can no longer be used since four possible data input signal voltage levels are required for correspondence with the four possible stored charge levels.
Existing sense schemes for multilevel storage systems employ a plurality of fixed reference voltage levels for comparison with the data input signal voltage level corresponding to the memory cell charge level. Referring to the four possible charge level system described above, a typical sense scheme employing a plurality of fixed reference voltage levels might work as follows. Data input signal voltage levels of 0, 2, 4, and 6 voltage units correspond to memory cell charge levels of 0, 2, 4, and 6 charge units respectively. The relative magnitudes of the data input signal voltage level and each of three fixed reference voltage levels are compared. Three appropriate fixed reference voltage levels would be 1, 3, and 5 voltage units. By determining whether the data input signal voltage level is higher or lower than each of the three fixed reference voltage levels, the memory cell charge level may be determined. Since each memory cell charge level corresponds to one of the four states represented by two data bits, the stored data may be read. As the amount of data stored per cell increases, the number of reference voltage levels required to read the data state of a memory cell also increases. Thus, in deciding whether or not to use a multilevel storage system, one must weigh the factor of increased storage cell density against the increased complexity of the sense scheme for reading the data state of a memory cell.
Factors to be considered in evaluating a multilevel storage system include circuit space, performance, and required signal characteristics. The increased complexity of the sense scheme in a multilevel storage system may require mor circuit devices and hence a greater increase in circuit space than is saved by the increase in overall storage density. This is a particularly important consideration in the production of miniature, high density integrated circuit chips where chip space is at a premium. In addition, the increased complexity of the sense scheme in a multilevel storage system may reduce the speed with which a memory cell may be read or written. Finally, the required signal characteristics of a multilevel storage system must also be considered. As the number of possible data input signal voltage levels is increased, the magnitude of voltage separating such voltage levels decreases. The ability to differentiate between voltage levels then becomes more difficult since less signal noise is required to cause a misinterpretation of a voltage level. For one device cell dynamic memories, a high ratio of memory cell capacitance to signal line capacitance is thus desired because such will allow for a broad range of possible stored charge levels at which signal noise will not interfere with system operation.
It is therefore desirable to create an improved sense circuit for a multilevel storage system in which the previously described factors weigh more favorably in considering the use of such a multilevel storage system.